1. Field of the Invention
The present invention relates to a semiconductor memory device using memory cells each storing information in a capacitor having dielectric material sandwiched by two electrodes, and particularly relates to a semiconductor memory device configured to perform “forming” for the capacitor of each memory cell in an arbitrary area of a memory cell array including a plurality of the memory cells each having the capacitor.
2. Description of Related Art
A DRAM (Dynamic Random Access Memories) which is a typical semiconductor memory device has been conventionally widely used. A memory cell of the DRAM is composed of a capacitor formed of dielectric material. Meanwhile, research and development of various non-volatile RAMs as semiconductor memory devices have been advanced. One of the non-volatile RAMs is a RRAM (Resistance Random Access Memory) using a variable resistance element. Generally, in an information processing system, it is desirable to provide both a DRAM temporarily storing data used in processing and a non-volatile RAM storing program and table data. Then, if a configuration in which both the DRAM and the non-volatile RAM are implemented on a single chip is employed, large advantages for miniaturization of devices and for manufacturing cost can be obtained.
In order to achieve a semiconductor memory device in which the DRAM and the non-volatile RAM are implemented on a single chip, memory cell fabrication techniques common between manufacturing processes of the DRAM and the non-volatile RAM have been conventionally known. For example, Patent Reference 1 discloses a technique to form capacitors used in the DRAM and capacitors used in the non-volatile RAM on conductive oxide electrodes having the same structure. Patent Reference 2 discloses a technique to form capacitors used in the DRAM and capacitors used in the non-volatile RAM on lower electrodes and barrier layers respectively having the same structure.    Patent Reference 1: Japanese Patent Application Laid-open No. H7-94681    Patent Reference 2: Japanese Patent Application Laid-open No. H9-82914
However, even when employing either of the techniques disclosed in the above Patent References 1 and 2, at least both making processes for the DRAM and the non-volatile RAM need to be performed in series in implementing them on a single chip because of a difference in material of dielectric films. As a result, the manufacturing process becomes complex, which causes problems including a decrease in yield and an increase in cost. Also, there is a problem that regions of the DRAM and the non-volatile RAM cannot be arbitrarily set after the manufacturing process and thereby it is difficult to flexibly apply to various applications.